chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
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chipsalliance.github.io/verible ↗github.com/chipsalliance/verible ↗
Worth your time
rules reportOutside contributors get real replies here, and their work gets merged. Replies are slow here: typically 15.5 days, beyond your 7-day budget.
31 of 44outside PRs merged (70%)
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